1. Field of the Invention
The present invention relates to a structure and method for operating an array of memory cells. More specifically, the present invention relates to a charge pump for driving word lines of an array of memory cells.
2. Discussion of Related Art
FIG. 1 is a circuit diagram of a conventional dynamic random access memory (DRAM) cell 100. DRAM cell 100 includes n-channel transistor 101, capacitor 102, word line 103 and bit line 104. In general, data is written to DRAM cell 100 by applying a high voltage to word line 103, thereby turning on transistor 101. A voltage representative of a data value is then applied to bit line 104. In response, capacitor 102 stores a charge representative of the data value. For a logic high voltage, it is desirable for a relatively high voltage to be applied to capacitor 102. To accomplish this, a boosted word line voltage is applied to word line 103 when accessing DRAM cell 100. The boosted word line voltage has a value of 1.5 times the V.sub.CC supply voltage. As a result, the voltage applied to capacitor 102 is approximately equal to the V.sub.CC supply voltage. FIG. 2 is a graph showing the variation of the boosted word line voltage V.sub.WL with respect to variations in the V.sub.CC supply voltage.
As a general rule, the V.sub.CC supply voltage is allowed to vary +/-10 percent. Thus, a V.sub.CC voltage supply having a nominal voltage of 5 Volts can vary from 4.5 volts (V.sub.CCMin) to 5.5 Volts (V.sub.CCMax). If the V.sub.CC supply voltage has a value of 4.5 Volts, the word line voltage is boosted to 6.25 Volts, thereby enabling an adequate voltage to be applied to capacitor 102. If the V.sub.CC supply voltage has a value of 5.5 Volts, then the boosted word line voltage has a value of about 8.25 Volts. The gate oxide of transistor 101 must therefore be designed to handle 8.25 Volts during normal operating conditions. As a result, the required thickness of the gate oxide of transistor 101 can be relatively thick. If all of the transistors in the device implementing DRAM cell 100 are designed to have the same gate oxide thickness, then the speed of the device may be slowed down by this thicker gate oxide. Otherwise, multiple gate oxide thicknesses may be required, thereby complicating the process used to fabricate the memory array.
FIG. 3 is a circuit diagram of a static random access memory (SRAM) cell 200. SRAM cell 200 includes cross coupled n-channel transistors 201-202, n-channel access transistors 203-204, load resistors 205-206, word line 207 and bit lines 208-209. In general, SRAM cell 200 is accessed by applying a high voltage to word line 207, thereby turning on access transistors 203-204. Voltages representative of a data value are then applied to bit lines 208-209. In response, one of transistors 201-202 is turned on and the other one of transistors 201-202 is turned off. The word line voltage is then de-asserted low, thereby latching a data value into transistors 201-202. One node stores a logic high voltage V.sub.H, and the other node stores a logic low voltage V.sub.L. In some SRAM circuits, the word line voltage is pumped to a voltage equal to V.sub.CC +1 volt, such that the voltage V.sub.H is equal to V.sub.CC +1 Volts-V.sub.tb, where V.sub.tb is the back bias voltage applied to access transistor 203 (or 204). Because V.sub.tb is typically about 1.5 volts, the voltage V.sub.H is equal to V.sub.CC -0.5 Volts. FIG. 4 is a graph illustrating the variation of the boosted word line voltage V.sub.WL for variations in the V.sub.CC supply voltage.
Again, the V.sub.CC supply voltage can vary +/-10 percent, between 4.5 volts (V.sub.CCMin) and 5.5 Volts (V.sub.CCMax) . If the V.sub.CC supply voltage has a value of 5.5 Volts, then the boosted word line voltage has a value of about 6.5 Volts. The gate oxide of access transistors 203-204 must therefore be designed to handle 6.5 volts during normal operating conditions. As a result, the gate oxide of access transistors 203-204 must be relatively thick. If all of the transistors in the device implementing SRAM cell 200 are designed to have the same gate oxide thickness, then the speed of the device will be slowed down by this thicker gate oxide. Otherwise, multiple gate oxide thicknesses may be required, thereby complicating the process used to fabricate the memory array.
It would therefore be desirable to have a circuit which boosts the word lines high enough to improve memory access characteristics, but not so high as to require a thick gate oxide.